1) Field of the Invention
This invention relates generally to the structure and fabrication of semiconductor devices and to a method of producing a silicon thin film, in particular, to a structure and method of forming a semiconductor on isolation wafer and more particularly to structure and method of forming a semiconductor on isolation wafer using strained layers.
2) Description of the Prior Art
There are various method for producing a SOI wafer. The SIMOX (Separation by IMplantation of OXygen) method uses a technique for forming a silicon oxide layer in a silicon substrate by implanting oxygen ions into the silicon substrate from its surface and then annealing the resultant substrate at a high temperature to form the silicon oxide layer at the portion where the oxygen ions have been implanted. In this method, the energy for implanting oxygen ions and the dose of the same cannot be set arbitrarily, but they are fixed to approximately constant conditions. Accordingly, it is difficult to set arbitrarily the thickness of the silicon film or that of the oxide film formed by ion implantation in the production of a SOI wafer.
The Eltran™ process by Canon uses a splitting water jet to split a bonded substrate structure.
Also, there are several types of semiconductor bonding method. The first one is referred to as “bonding and polishing SOI” method.
In the “bonding and polishing SOI” method, two silicon wafers at least one of which has been oxidized, are previously prepared, bonded to each other at room temperature and annealed, and then polished from its one side, to leave a silicon film of a desired thickness on the silicon oxide layer. According to this method, both the thickness of the silicon layer and that of the implanted oxide layer can be set arbitrarily. In this method, however, as means of making a thin film of a silicon layer are solely used grinding and polishing. Accordingly, it is difficult to obtain a thin film of a uniform several hundred nm thickness because the limitations of the original thickness accuracy and polishing accuracy in the silicon wafer.
As the measures to overcome the above difficulty, a technique for forming an ultrathin film (100 nm thick or less) uniformly in which thickness distribution of a SOI film is measured instantly and dry-etching is performed relatively heavily at regions where the film is rather thick while dry-etching is performed relatively lightly at regions where the film is rather thin has been reported. This technique is referred to as PACE (Plasma Assisted Chemical Etching). The PACE system includes two units separated from each other: a unit for measuring instantly thickness of a SOI film at in-plane multiple points (10000 points or more) and a unit for performing plasma etching. The unit for performing etching has a plasma generating portion in the form of a nozzle and is designed in such a manner that the nozzle can move over a wafer along its surface and generate plasma according to the measurements of the thickness of the SOI layer so as to etch, for example, the rather thick regions relatively heavily. This technique allows the control of the etching amount from region to region within the wafer surface and hence the control of the absolute value and uniformity of the film thickness. However, the surface having been subjected to plasma-assisted etching has etching damage remaining thereon; accordingly, in many cases, the surface of the SOI layer is subjected to polishing so as to remove its damaged layer. This polishing operation may cause non-uniformity again in the film thickness of the SOI layer which has just been made uniform.
The more relevant technical developments in the patent literature can be gleaned by considering the following.
U.S. Pat. No. 6,653,209 Yamagata—Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
U.S. Pat. No. 6,649,492 Chu, et al.—Strained Si based layer made by UHV—CVD, and devices therein.
U.S. Pat. No. 6,723,541 —Sugii, et al.—shows a method of producing semiconductor device and semiconductor substrate.
U.S. 20030207545 A1—Yasukawa—An SOI substrate is provided with: a support substrate; a single crystal silicon layer disposed above one surface of the support substrate; an insulation portion disposed between the support substrate and the single crystal silicon layer, the insulation portion comprising a single layer of an insulation film or a lamination structure of a plurality of insulation films.